This invention relates to the interface between a main processor and co-processor, particularly to a control method suitable for the speed-up of operand fetching from memory and also for storing the operational result in memory in executing a co-processor instruction.
A trend of computer system design, in which the main processor has basic arithmetic processing functions, is the provision of a co-processor which supports special arithmetic functions required for the system in the form of expanded main processor instructions. In the interface system for the co-processor requesting two bus cycles for fetching an operand into the co-processor, i.e., from memory to main processor, and then from main processor to co-processor, as described in the MOTOROLA 68020 User's Manual (referred to as Citation-1 hereinafter), there is a shortcoming in that a great linkage time is required for the main processor and co-processor. Although the linkage time does not appear to be critical when the memory access time is incomparably greater than the data transfer time between the main processor and co-processor, the speed-up of operation for the system with two-bus cycles is limited when a cache memory system or fast memory system is employed.
In the case of the co-processor described in the INTEL iAPX 86 REFERENCE MANUAL (referred to as Citation-2 hereinafter), the co-processor becomes the bus master occupying the bus to transfer data from the storage unit. This system allows data transfer in one bus cycle, but needs individual hardware for decoding the instruction and calculating the effective address, which could be shared with the main processor, and further needs the bus interface for the bus master. The instruction architecture of the case of Citation-1 results in double the hardware needed by the co-processor.